1. Field of the Invention
The present invention relates generally to memory devices, and more particularly to, systems and methods for providing high voltage to memory devices.
2. Description of the Related Art
Previous memory systems use Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices as Non-Volatile (NV) storage elements in the NV EEPROM or Flash Memories. These prior memory systems rely on the usage of SONOS devices with thicker gate oxide layers (e.g., 110 A) for the high voltage operations related to programming and erasing of the NV Flash Macro.
Some prior memory devices have a voltage gate oxide (Vgox) maximum of 7.3 volts and a junction voltage (Vjunc) of 10.5 volts. Other prior memory devices have a maximum Vgox of 8.1 volts and a Vjunc of 7.6 volts. To make these memory devices compatible with high voltage levels, these memory devices had to be laid out as ring transistors.
More recent memory devices have a maximum Vgox of 6.9 volts and a Vjunc of 11.3 volts, while some other memory devices have a maximum Vgox of 7.7 volts and a Vjunc of 11.3 volts. While the supply voltage levels are decreasing in newer technologies, the NV memory devices still require relatively high voltage for NV operations. In other words, these voltages are still too high to be directly supported by memory devices with thinner gate oxide thicknesses (e.g., gate oxide thicknesses of 55 A) since memory devices with thinner gate oxide thicknesses can typically only handle low voltage. For example, memory devices with a gate oxide thickness of 55 A typically can handle a maximum of 2.5 volts. Thus, prior memory systems do not utilize memory devices with a gate oxide thickness of 55 A for high voltage applications.
Furthermore, as the interest for smaller and faster devices has increased, interest in SONOS device scale down has increased as well. However, the aforementioned high voltage signals used on devices with thicker gate oxides may cause stresses on the devices with thinner gate oxides. Although additional devices can be employed to mitigate such stresses, inclusion of such devices may increase costs and complicate circuit fabrication.